`include "cpu_def.vh"

module cp0_forward(
  input [ 4:0] de_cp0_rreg_num,
  input [ 2:0] de_cp0_rsel    ,

  input        ex_cp0_wen     ,
  input [ 4:0] ex_cp0_wreg_num,
  input [ 2:0] ex_cp0_wsel    ,
  input [31:0] ex_cp0_wdata   ,

  input        wb_cp0_wen     ,
  input [ 4:0] wb_cp0_wreg_num,
  input [ 2:0] wb_cp0_wsel    ,
  input [31:0] wb_cp0_wdata   ,

  output [ 1:0] sel_cp0_rdata, // select cp0 read data in de stage
                               //* 00: cp0 read date from de stage
                               //* 01: cp0 write data from ex stage
                               //* 10: cp0 write data from wb stage
  output [31:0] cp0_rdata_ex ,
  output [31:0] cp0_rdata_wb 
);

  wire de_ex_rel = 
    (de_cp0_rreg_num == ex_cp0_wreg_num) && 
    (de_cp0_rsel == ex_cp0_wsel) && ex_cp0_wen;

  wire de_wb_rel = 
    (de_cp0_rreg_num == wb_cp0_wreg_num) && 
    (de_cp0_rsel == wb_cp0_wsel) && wb_cp0_wen;

  assign sel_cp0_rdata[0] = de_ex_rel;
  assign sel_cp0_rdata[1] = !de_ex_rel && de_wb_rel;


  assign cp0_rdata_ex = ex_cp0_wdata;
  assign cp0_rdata_wb = wb_cp0_wdata;

endmodule